College of Engineering University of Wisconsin-Madison
Electrical and Computer Engineering The Fountain
ECE 751 Embedded Computing Systems

Last modified Monday, 25-Nov-2019 16:09:20 CST

Contact Information
Course Description
Lecture Notes
Paper Reviews and Presentations
Course Schedule
Useful Links


Contact List:

Mailing list (only registered students can send messages):


Prof. Mikko Lipasti
Office: 3621 Engineering Hall
Office Hours: Tue 4-5pm, Wed 10-11am

Course Description

This course examines the design and analysis of high-performance embedded computing systems. Topics covered include embedded applications, embedded processors and multiprocessors, embedded system design and simulation, embedded hardware design, configurable/reconfigurable embedded systems, embedded compilers and tool chains, run-time systems, application design and customization, hardware and software co-design, and low-power design.

Note that there may appear to be some topical overlap with ECE 750, ECE/CS 752, and ECE/CS 757. However, the topics chosen and the approach and emphasis placed on them in this course will differ substantially from their treatment in these other courses.

ECE/CS 552 is a firm prerequisite; if you are a transfer or graduate student without this course background, you should be very familiar with logic design and should have already designed a working instruction set processor. You should be very familiar with pipelined execution, data hazards, and basic control speculation, along with simple cache memories and virtual memory. If you do not have this background, you will have to do some catch-up reading to keep up in this course.

Refer to the course syllabus for additional details

There is no course textbook. A useful reference is High-Performance Embedded Computing, by Wayne Wolf, ISBN 012369485X.

You can read the book online using this link through the Wendt Library (requires UW-Madison NetID to login).

Lecture Notes

NOTE: Lecture notes will be updated as semester progresses

Paper Presentations and Reviews

Please follow these guidelines when preparing your paper reviews.

Paper reviews are to be submitted via Learn@UW by 11am the day of scheduled discussion, as listed in the table below.

Paper presentations should adhere to the following guidelines:

Course Schedule:

Refer to bibliography for paper references.

Semester Schedule

Date Topic Review Read Presenter
9/15,9/17 752/757 Review None None None
9/22 Embedded CPUs [3] [4] None
9/24 Embedded CPUs [5] [6] Gautam[6]
9/29 Embedded CPUs [7] [8] Chandana [7], David [8]
10/1 ISA Customization [10] [9] Nirvedh [10]
10/6 ISA Customization [11] [13] Vinay [11]
10/8 No lecture
10/13 ISA Customization [12] [14] None
10/13 Project proposal due
10/15 Network on Chip [17] [15][16] Liang Zhang [17]
10/20 Embedded Software [21] [18] Peng Liu [21]
10/22 Embedded Software [22] [19][20] Deepinder [20], Bharadwaj [22]
10/27 Embedded O/S [25] [23] Shashank [25]
10/29 Embedded O/S [26] [24] Mikkel Nielsen [26]
10/29 Embedded Multiprocessors and Heterogeneous Chips [28] [27] Wasim Shaikh [28]
11/3 Accelerators [33] [34] Di Wu [33]
11/5 Accelerators [31] [29] Yao Song [31]
11/10 Accelerators [30] [36][37] Jonathan Mathews [30], Brian Coutinho [37]
11/12 Accelerators [35] [38] Mojes Koli [35], Gokul Ravi [38]
11/12 Heterogeneous Memory [39] (note due date)
11/17 Heterogeneous Memory [41] [40] Anilkumar Ranganagoudra [39], Ajay Sekar [41]
11/17 Project progress report due
11/19 Scratchpads and Caches [42] [43] Sharmila Shridhar [42], Vijay Vijayaraghavan [43]
11/24 Scratchpads and Caches [44] [45] Keshav Mathur [44]
11/24 Security [46] TBD Kenneth Siu [46]
11/26 Thanksgiving Break
12/1 Project Presentations
  1. PENN: Programmable Engine For Neural Networks (Vinay, Sharmila, Anil, Chandana)
  2. MIMD Processors for Vision (Vijay, Bharadwaj, Ajay, Deepinder)
  3. Video Transcoder on CPU+FPGA Platform (Peng, Yao, Di, Liang)
12/3 Project Presentations
  1. Hardware Accelerator for Hot-word Recognition (Gautam, Jonathan, Wasim, Mojes)
  2. Caches for Accelerators (Brian, Keshav, David, Gokul)
  3. Neural Processing Unit on Zedboard (Shashank, Nirvedh, Mikkel, Kenneth)
12/8, 12/10 No lecture (project work)
12/15 Final exam review
12/15 Project reports due
12/18 Final exam, 5:05pm


To check your recorded grades, log in to Learn@UW using your NetID and password (same as your as email username or your login), click on "2015 - FALL" and then 751.


There will be a final exam held on Dec. 18, 2015 from 5:05pm-7:05pm. Please plan your travel accordingly.

The scope for the exam is the following readings (a subset of the papers reviewed during the semester): [3][5][11][21][22][26][28][30][31][35][41][42][46].

Here is a sample exam from a prior semester. The sample exam has a different scope but should give you a sense of the exam structure and types of questions that will be asked on the final.

The exam is open notes/papers.

The exam will be held in EH2540 from 5:05pm-7:05pm on Friday, 12/18/2015.

Course Project Information

For the course project you will do a research-focused project. This may involve reimplementing an idea proposed in a paper we read in the class (or outside of class) or trying something new that you have come up with. More details to follow.

You will be required to do the following for the final project:

Note that originality is not required (however, it is encouraged) for the project, nor are "positive" results (in other words, you will not be penalized for finding that a proposed scheme does not work). You will be graded based on your effort and on the quality of your presentation and report.

Suggested project topics

Here are some guidelines for the project report.

Presentation schedule: Please see schedule above.


Digilent Zynq board information

There are Digilent Zynq boards available for prototyping your course projects. The boards contain 512MB of DDR3 memory, a Zynq-7020 FPGA that contains two ARM cores, and a large number of peripherals. More information on the boards is available from the Digilent product page There is also an active developer community at the Zedboard site. You can download the Vivado webpack tools from Xilinx.

Benchmark Information

WARNING: some of these gzipped tar files are quite large. Make sure you have plenty of disk space (several hundred MB in some cases).

SPEC2006 source code distribution (licensed only for use at Univ. of Wisconsin).
SPEC95 little-endian PISA binaries (including go for hw2)
SPEC2000 Integer EIO Traces for sim-outorder/alpha
libexo/libexo.c patched source file that you may need for these EIO traces to work correctly
SPEC2000 Integer binaries and runscripts for sim-outorder/alpha
SPEC2000 Floating Point EIO Traces for sim-outorder/alpha
SPEC2000 Floating Point binaries and runscripts for sim-outorder/alpha

The EIO traces can be used with simplescalar/alpha running on linux. See README.eio within the simplescalar distribution. You will have to compile simplescalar to use the alpha instruction set by typing "make config-alpha". The runscripts/binaries can be used on any little-endian machine (linux/intel). I don't think they will work on the CAE Sun workstations, which are big-endian.

Useful Links:

Note: if you have trouble accessing this page, contact Mikko Lipasti (